MemryX Inc., a company delivering production AI inference acceleration, today announced its strategic roadmap for the\u00a0MX4. The next-generation accelerator is engineered to scale the company\u2019s \u201cat-memory\u201d dataflow architecture from edge deployments into the data center, leveraging\u00a03D hybrid-bonded memory\u00a0to eliminate the industry\u2019s most pressing bottleneck: the \u201cmemory wall.\u201d<\/p>\n
MemryX is currently in production with its\u00a0MX3 silicon, delivering >20\u00d7 better performance per watt than mainstream GPUs for targeted AI inference applications. With MX4, MemryX is extending that production-proven foundation to address data center workloads increasingly constrained not by compute, but by memory capacity, bandwidth, and energy efficiency.<\/p>\n
MemryX has now signed an agreement with a next-generation 3D memory partner to execute a dedicated\u00a02026 test chip program, validating a targeted ~5\u00b5m-class hybrid-bonded interface and direct-to-tile memory integration. The partner is not disclosed at this time.<\/p>\n
The announcement comes as the semiconductor industry increasingly prioritizes deterministic inference architectures for the next era of AI processing, reinforced by recent multibillion-dollar licensing and investment activity across AI hardware\u2014such as\u00a0Nvidia\u2019s $20B deal with Groq, which underscores\u00a0the massive strategic value of\u00a0efficient inference solutions. While the first generation of dataflow solutions proved the\u00a0efficiency of 2D SRAM, MemryX is moving into the third dimension to address the power, cost, and complexity constraints of frontier AI workloads.<\/p>\n
Software Continuity: Leveraging the MX3 Compiler Foundation<\/p>\n
MemryX plans to leverage its mature, production-proven MX3 software stack \u2014 including its compiler and runtime \u2014 as the foundation for MX4. While MX4 introduces new capabilities to support larger memory footprints and data center-scale configurations, the roadmap is designed to preserve key elements of the MX3 programming model and toolchain to accelerate adoption and shorten time-to-deployment for existing and new customers.<\/p>\n
Beyond LLMs: Powering Frontier Inference<\/p>\n
While Large Language Models (LLMs) remain a priority, the data center is rapidly evolving toward\u00a0Large Action Models (LAMs), high-resolution multimodal vision, and real-time recommendation engines. These \u201cfrontier workloads\u201d require massive memory capacity and predictable throughput that traditional 2.5D HBM-based architectures struggle to provide efficiently.<\/p>\n
The MX4 addresses this by physically bonding high-bandwidth memory directly to compute tiles, shifting the focus from data movement back to high-efficiency computation.<\/p>\n
The Asynchronous Advantage: Scalability Without Bottlenecks<\/p>\n
The MX4 represents a fundamental departure from synchronous chip designs. Many current accelerators rely on a global synchronous clock, which can introduce clock skew and thermal challenges as designs scale using 3D stacks.<\/p>\n
Like the MX3, the MX4 utilizes a\u00a0data-driven producer\/consumer flow-control model\u00a0and avoids the centralized memory bottlenecks common in traditional architectures by enabling direct interfaces from 3D memory to compute tiles. However, rather than using 2D embedded SRAM like the MX3, the MX4 directly connects computing tiles to 3D memories without using single shared controllers.<\/p>\n
Asynchronous Scaling:\u00a0Tiles operate independently, processing only when data is available and downstream consumers are ready. This naturally manages backpressure and reduces the switching overhead and clocking complexities inherent in synchronous architectures.<\/p>\n
Direct-to-Tile 3D Interface:\u00a0By targeting a ~5\u00b5m-class hybrid bonding pitch, MX4 enables a distributed vertical interconnect in which individual compute engines access memory layers directly\u2014without relying on a single shared memory controller used by today\u2019s HBM-based designs.<\/p>\n
Technology Agnostic:\u00a0The architecture is designed to support multiple 3D direct to memory formats, including today\u2019s stacked DRAM and emerging FeRAM-class technologies.<\/p>\n
Roadmap to Production<\/p>\n
2026:\u00a0Dedicated test chip (in partnership with a 3D memory provider) to validate ~5\u00b5m-class hybrid bonding interface and direct-to-tile 3D memory integration<\/p>\n
2027: First MX4 customer sampling<\/p>\n
2028: Production release, scaling from single-chip systems to multi-chip data center arrays supporting >1TB memory configurations<\/p>\n
\u201cThe industry has recognized that deterministic dataflow is a compelling path forward for AI inference, but both efficiency and scale are critical,\u201d said\u00a0Keith Kressin, CEO of MemryX. \u201cBy combining our production-proven architecture\u2014including an asynchronous flow model\u2014with 3D hybrid bonding, we are removing the physical barriers to power-efficient trillion-parameter scalability. We aren\u2019t just building a faster chip; we are building a more practical roadmap for the future of AI.\u201d<\/p>\n
Learn More<\/p>\n
To review the architectural foundation of the MX4, visit the MemryX MX3 Architecture Overview:\u00a0https:\/\/developer.memryx.com\/architecture\/architecture.html\u00a0<\/p>\n
Specifications, partners, and timelines are targets and subject to change.The post MemryX Unveils MX4 Roadmap first appeared on AI-Tech Park.<\/p>\n","protected":false},"excerpt":{"rendered":"
MemryX Inc., a company delivering production AI inference acceleration, today announced its strategic roadmap for the\u00a0MX4. The next-generation accelerator is engineered to scale the company\u2019s \u201cat-memory\u201d dataflow architecture from edge deployments into the data center, leveraging\u00a03D hybrid-bonded memory\u00a0to eliminate the industry\u2019s most pressing bottleneck: the \u201cmemory wall.\u201d MemryX is currently…<\/p>\n
The post MemryX Unveils MX4 Roadmap<\/a> first appeared on AI-Tech Park<\/a>.<\/p>\n<\/div>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"site-container-style":"default","site-container-layout":"default","site-sidebar-layout":"default","disable-article-header":"default","disable-site-header":"default","disable-site-footer":"default","disable-content-area-spacing":"default","footnotes":""},"categories":[4,1],"tags":[3],"class_list":["post-359","post","type-post","status-publish","format-standard","hentry","category-ai","category-ai-and-ml","tag-ai"],"yoast_head":"\n